This invention relates to field programmable gate array (“FPGA”) integrated circuits and the like. More particularly, the invention relates to FPGAs that are better adapted for use in applications involving the types of data processing techniques that are sometimes referred to as forward error correction. Another term that is sometimes used for at least some FPGAs is programmable logic device or PLD. The terms FPGA and PLD are used interchangeably herein.
FPGAs are typically designed to be relatively general-purpose devices. An FPGA is designed so that it can support any of many different possible uses. Each user of the FPGA can then program or configure the device to perform the particular task or tasks which that user needs to have the FPGA perform. The FPGA can be manufactured in larger quantities at lower unit cost because it can be sold for many different uses.
An area of increasing interest for use of FPGAs is in high-speed serial data communication. The speeds of interest for such communication are constantly increasing. Also, the number of different protocols that may be used for such communication is similarly increasing. Some of these protocols involve the technology known as forward error correction or FEC. FEC may involve sending each block of real user data with some additional bits of information that are computed from the user data. At the receiver, these additional bits can be used to determine whether there are any errors in the user data as received, and also to correct such errors (provided the number of errors does not exceed the limit of the error-correction capability of the FEC technique being employed).
As data rates become very high, it becomes increasingly difficult to perform FEC in the general-purpose core logic of an FPGA. For example, at very high data rates such as 10 Gbps (gigabits per second), 12.8 Gbps, or higher, very wide data buses may be necessary to permit FEC in FPGA core logic. This may have a number of disadvantages such as using up large amounts of core logic resources and necessitating long signal paths that can force operation of the FPGA at a lower speed. The present invention allows FPGAs to support FEC in a different way.